Verilog processor for Notepad++. Current features:
– Instantiate a module
– Insert registers/wires from a module
– Generate a test bench template
– Automatically inserts a default header for a test bench
– Insert a clocked always block
v1.2.0 now supports ANSI and non-ANSI module declarations.
To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C. This selects the module and parses its components. After this, all other functions are available.
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