naga EDA devotes to provide useful electronic design tools in C++ and, especially, Python. The current release contains naga.Verilog, a Verilog parser. Please visit project homepage http://naga-eda.org for more information The SourceForge Speed Test measures Latency/Ping, Jitter, Download Speed, Upload Speed, Buffer Bloat, and Packet Loss. Upon completion, you can view detailed reports about your […]
VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book If you are like the rest of our user community, your IT […]
FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits. 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 129 Reviews Unrivaled value & reliability in […]
This software can be used to very simple show how to 8051 working. You can very simple conect to procesor gates, LED-s, switch …,and load software to procesor and see rezult, how all device will work. My site: www.kloszi.prv.pl I’m looking for a job.. You’re probably paying too much for cell phone service. Wirefly compares […]
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. Cloudbased voice solutions are common in enterprise networks and frustrating for operations teams to manage. Simplify VoIP monitoring by having a […]
This is a tool developed by 2nd yr CSE B.Techs at IIT Guwahati.We have designed a software in C++ language which,given some design specifications of an analog amplifier generates a netlist file in the current folder which can be opened in LTSpice. SolarWinds Storage Resource Monitor (SRM) gives you multi-vendor storage performance monitoring and alerting […]
MyHDL is a Python package for using Python as a hardware description and verification language. Cloudbased voice solutions are common in enterprise networks and frustrating for operations teams to manage. Simplify VoIP monitoring by having a proactive analysis of on-prem, hybrid and UCaaS voice services. Try the ThousandEyes VoIP monitoring solution today, free.
Power consumption analysis tools for embedded systems. MARTE to AADL model transformation with ATL for tools interoperability. More info on the project at http://sourceforge.net/apps/trac/lab-sticc/ 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 129 Reviews Unrivaled value & reliability in one solution Unlimited Calls/SMS/Conferencing/Fax Trusted by 350,000+ Businesses
simple digital logic circuit simulator, using only NAND gates. written as a standalone app for your web browser The SourceForge Speed Test measures Latency/Ping, Jitter, Download Speed, Upload Speed, Buffer Bloat, and Packet Loss. Upon completion, you can view detailed reports about your connection. This HTML5 speed test does not require Flash or Java, and […]
We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. […]