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VHDL Design Verification Tools

Posted on April 9, 2013January 5, 2018 by Robin Ding Leave a comment Compilers, Modeling, Testing

This project contains a set of tools for formal verification and static analysis of VHDL design.

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Website	http://vhdlverif.sourceforge.net
Tags	Compilers Modeling Testing
License	GNU General Public License version 2.0 (GPLv2)
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